1. Field of the Invention
This invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method for fabricating a cylindrical capacitor of a DRAM cell.
2. Description of the Related Arts
The development of the semiconductor industry has always followed that of the Dynamic Random Access Memory (DRAM) technology. A conventional DRAM cell consists of a transistor and a capacitor. The source of the transistor is connected to a corresponding bit line, the drain is connected to a storage electrode of the capacitor, and the gate is connected to a corresponding word line. An opposite electrode of the capacitor is biased with a constant voltage source. A dielectric layer is arranged between the storage electrode and the opposite electrode. As known to those skilled in the art, the storage capacitor is provided for data storage. Therefore, a large capacitance is required for the capacitor to prevent data loss and to lower the refresh rate.
For a conventional DRAM of less than 1 MB capacity, a two-dimensional capacitor structure is utilized for data storage. This capacitor structure is well known as a planar-type capacitor. However, in order to provide a capacitance large enough for data storage, the planar-type capacitor occupies a very large base area. This structure cannot therefore be applied in a high-density DRAM process. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double stacked, fin structured, cylindrical, spread-stacked, and box structured capacitors.
The conventional fabrication steps of a cylindrical capacitor for a DRAM cell will be described in accompaniment with the drawing of FIG. 1A through FIG. 1G. Referring to FIG. 1A, a field oxide 12 is formed on a semiconductor substrate 10 for defining active regions and isolation regions. Then a MOSFET transistor is formed over the active region. The transistor can comprise: a gate oxide layer 14, gate electrode 16, source 24A, and drain 24B. The gate electrode 16 is surrounded by insulating spacers 18.
As shown in FIG. 1A, the transistor is covered by a first insulating layer 30, for example a borophosphosilicate glass (BPSG) layer, which is etched to form a contact hole (not shown in the figure) to expose the drain region 24B of the transistor. Then a first conductive layer is formed over the first insulating layer and fills the contact hole, thereby electrically connecting the drain region 24B. This conductive layer is patterned to form a bit line of the memory device (not shown in the figure). Then a second insulating layer 32, for example a BPSG layer, is deposited over the first insulating layer 30 and the exposed bit line. After the second insulating layer is planarized by reflow, a first silicon nitride layer 34 is deposited on it as a hard mask. The first nitride layer 34 preferably has a thickness of about 1500 .ANG..
Referring to FIG. 1B, as a beginning step in forming electrode contacts to the source region, an opening 35 is formed over the source 24A through the first nitride layer 34. Then a second silicon nitride layer 36 is formed over the first nitride layer 34 and the second insulating layer 32, which is then anisotropically etched to form nitride spacers 36A on the sidewalls of the opening 35.
Referring to FIG. 1C, using the first nitride layer 34 and the nitride spacers 36A as an etch mask, a contact hole 37 is etched through the first and the second insulating layers 30, 32 exposing the sources 24A. The contact hole 37 can be formed by using anisotropic etching techniques such as reactive ion beam (RIE) etching. The sidewall spacers 36A allow the contact hole 37 to be more precisely defined thus allowing the capacitor to be further miniaturized.
Referring to FIG. 1D, oxide spacers 38 are formed on the sidewalls of the contact hole to prevent shorting between the capacitor and the word lines. The oxide spacers are fabricated by forming a conformal silicon oxide layer using low pressure chemical vapor deposition (LPCVD). Then the conformal silicon oxide layer is anisotropically etched. The conformal silicon oxide layer preferably has a thickness of 300 .ANG.. Next, a conductive layer 40 is formed over the first nitride layer 34 and fills the hole 37 thus forming an electrical connection to the contact region. The conductive layer 40 can be a doped polysilicon layer.
Referring to FIG. 1E, the conductive layer 40 is etched back to the first nitride layer 34 thus forming a conductive polysilicon plug 40A; or alternatively, the undesired portions of the conductive layer can be removed by chemical mechanical polishing (CMP) using the first nitride layer 34 as a stopping layer.
Thereafter, a conductive polysilicon layer is deposited over the polysilicon plug 40A and the first nitride layer 34, which is then patterned to form grooves that define areas for individual cell units. As shown in FIG. 1F, grooves 41 are formed between the adjacent cells thereby forming polysilicon islands 42 which connect to the aforementioned polysilicon plug 40A.
In order to increase the capacitance of the DRAM capacitor, the first nitride layer 34 is then isotropically etched through the groove 41 to thereby expose the bottom surface of the polysilicon islands 42. This isotropic etch is generally realized by wet etching techniques. However, since the wet etchant for silicon nitride attacks silicon dioxide as well, the oxide spacers 38 could be encroached or even broken through by the wet etchant, therefore damaging the polysilicon plug 40A.
Accordingly, it is necessary to develop methods of manufacturing cylindrical capacitors that can prevent the contact plug from being damaged by the wet etchant.